A display panel generally includes a liquid crystal (LC) panel and an organic light emitting diode (OLED) panel. A driving circuit cooperating with a backlight unit drives the LC panel to display image.
As shown in FIG. 1, a thin film transistor (TFT) array area 120 is arranged on an array substrate 100 of the LC panel, where signal lines and TFTs are arranged in the TFT array area 120. Bonding pad of a driving circuit board 130 is connected with the signal line of the array substrate through fanout lines 111, and the fanout lines are arranged on a fanout area.
The bonding pad is closely arranged on the driving circuit board 130, but the signal lines are dispersedly arranged in the TFT array area 120, namely distances between the bonding pad and different signal lines are different, which allows the fanout lines, connected between the bonding pad and the signal lines, to have different resistance values. A waveform of a signal changes because of different lengths and resistance values of the fanout lines, thereby affecting display quality of the LCD device. At present, a coiling is arranged in the fanout line to allow different lengths and resistance values of fanout lines to obtain even resistance values. As shown in FIG. 2, a bending section 112 is formed in the fanout line through the coiling, which increases length of the fanout line, and then increases the resistance value of the fanout line, thereby synchronizing the signals transferred by the fanout lines. The bending section 112 increases a height H of the fanout area, as a straight-line distance between two endpoints of the fanout line shortens, a length of a coiling arranged in the fanout line correspondingly becomes long. However, a gap space between the fanout lines is limited, thus, as the straight-line distance between two endpoints of the fanout line shortens, more bending sections are arranged to increase the length of the coiling of the fanout line (two bending sections are arranged in each of the fanout lines in FIG. 2), which increases the height H of the fanout area, thereby affecting a flame width of the LCD device, and further affecting design of narrow frame of the LCD device. Additionally, signal waveform distortion occurs not only in an impact of the resistance value of the fanout line, but parasitic capacitance is also an important impact factor. The FIG. 3 is a cross-section diagram of the fanout area of the LC panel, where a parasitic capacitor CLC is generated between a first conducting film 106 of the fanout line 111 of the array substrate 100 and an indium tin oxide (ITO) conducting film 201 of a color filter substrate 200, and between a second conducting film 104 of the fanout line 111 of the array substrate 100 and the ITO conducting film 201 of the color filter substrate 200, which causes the signal to delay. However, because lengths of the fanout lines are different, an overlapping area between the first conducting film and the ITO conducting film and an overlapping area between the second conducting film and the ITO conducting film, which correspond to different lengths of fanout lines, are correspondingly different. Thus, the parasitic capacitors are different, which causes different influences for the signal.